Method and system for filtering image data

ABSTRACT

A device that includes at least one memory unit adapted to store image data; the device is characterized by including a configurable filter adapted to apply de-ringing filtering and de-blocking filtering such as to filter image data retrieved from the at least one memory unit, whereas the device is adapted to repetitively determine a configuration of the configurable filter in response to received image data and to at least one mode selection rule and to configure the configurable filter in response to the determination. A method for filtering image data, the method includes receiving or defining filtering mode selection rules; and receiving image data; whereas the method is characterized by including repeating the stages of: determining a configuration of a configurable filter that is adapted to perform de-ringing and de-blocking filtering, in response to the received image data and to at least one mode selection rule; configuring the configurable filter in response to the determination; and filtering, by the configurable filter, image data.

FIELD OF THE INVENTION

The present invention relates to methods and systems for filtering imagedata and especially for performing de-ringing and de-blocking filtering.

BACKGROUND OF THE INVENTION

Methods and systems for compressing and transmitting media signals areknown in the art. Compressed digital video is largely becoming thepreferred medium to transmit to video viewers everywhere. Parts of theMoving Pictures Experts Group (MPEG) specifications are standardizedmethods for compressing and transmitting video. The TelecommunicationStandardization Sector of the International Telecommunication Union(ITU-T) also defines various compression standards including H.261,H.263, H.264 and the like.

In general, MPEG as well as ITU-T standards are used today fortransmitting video over terrestrial, wireless, satellite and cablecommunication channels and also for storing digital video.

Some standardized compression/encoding standards utilize variouscompression schemes, such as adaptive quantization, intra-frameencoding, inter-frame encoding, run length encoding and variable lengthcoding. Intra-frame coding takes advantage of spatial redundancies in apicture. Inter-frame coding takes advantage of temporal redundanciesfrom picture to picture in a video sequence. Inter-frame coding involvesmotion estimation and motion compensation. Motion estimation involvessearching, for each block (including N×M pixels, whereas N usuallyequals M), within a predefined area, a best matching block. The relativepositions of these blocks are referred to as motion vector. Motioncompensation involves calculating the differences between each block andthe best matching block and encoding said difference by a spatialtransformation, such as a Discrete Cosine Transform (DCT).

The block-based encoding has resulted in blocking artifacts. Theseartifacts appear at the boundary of adjacent blocks. This problem isusually more acute in low bit rate transmission systems, in whichsubstantially strong quantization operation is applied.

In order to overcome these blocking artifacts two type of de-blockingfilters were introduced. The first type is known as a post filter andthe second type is known as a loop filter (or in-loop filter). The firsttype is applied after the encoding process ends while the loop filter isapplied as a part of an encoding scheme. Encoders that include loopfilter are characterized by better image quality.

A typical de-blocking filter, and especially an H.264/MPEG-4 compliantde-blocking filter can apply different filtering operation (in otherwords—operate in various filtering modes) in response to a boundarystrength parameter. The different filtering modes differ by the strengthof de-blocking filtering applied to the image data.

De-ringing filtering removes sudden transitions from a frame. Thefiltering process usually starts by a threshold-acquisition stage duringwhich a maximal and a minimal pixel values within a group of pixels issearched. These values are used to calculate a threshold value. Thethreshold value is used to generate an index matrix in which value oneis assigned to pixels within the group that have a value that is greaterthen the threshold. The other pixels are assigned with a value of zero.The index matrix is then clipped.

Various de-blocking filters, de-ringing filters and a combination ofboth filters can be found in the following patents, patent applicationsand article, all being incorporated herein by reference: U.S. patentapplication publication number 2004/0076237 of Kadono et al.; U.S.patent application publication number 2001/0020906 of Andrews at al.;U.S. patent application publication number 2005/0024651 of Yu et al.;U.S. patent application publication number 2005/0123057 of MacInnis etal.; U.S. patent application publication number 2002/0118399 of Estevezet al.; U.S. patent application publication number 2004/0228415 of Wang;U.S. patent application publication number 2003/0021489 of Miura et al.;U.S. patent application publication number 2003/0219074 of Park et al.;U.S. patent application publication number 2005/0100241 of Kong et al.;U.S. patent application publication number 2005/0147319 of Deshpande etal.; U.S. patent application publication number 2004/0247034 of Zhong etal.; U.S. patent application publication number 2005/0053288 ofSrinivasan et al.; U.S. Pat. No. 6,950,473 of Kim et al.; and “AdaptiveDe-blocking Filter”, by P. List, A. Joch, J. Lainema, G. Bjontegaard andM. Karczewicz, IEEE transactions on circuits and systems for videotechnology, Vol. 13, No. 7, July 2003.

Each one of the de-blocking filtering and the de-blocking filtering isvery complex and requires many computational resources. Due to theircomplexities many prior art solutions use multiple hardware filters toperform these operations. Some prior art solutions provide a dedicatedde-blocking filter that is tailored to perform de-blocking filteringwhile another filter is tailored to perform de-ringing filtering. Thisapproach can provide a high-speed filter but it consumes a large amountof integrated circuit real estate.

There is a need to provide an efficient system and method for filteringimage data.

SUMMARY OF THE PRESENT INVENTION

A device and a method for filtering image data, as described in theaccompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 is a schematic diagram of a device, according to an embodiment ofthe invention;

FIG. 2 illustrates a configurable filter, according to an embodiment ofthe invention;

FIG. 3 illustrates a mode decision unit, according to an embodiment ofthe invention;

FIG. 4 illustrates a mode update unit, according to an embodiment of theinvention;

FIG. 5 illustrates an arithmetic unit, according to an embodiment of theinvention;

FIG. 6 illustrates a memory interface, according to an embodiment of theinvention; and

FIG. 7 is a flow chart of a method for performing de-ringing andde-blocking filtering, according to an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

According to an embodiment of the invention a device and method forfiltering image data is provided. The device includes at least onememory unit adapted to store image data. The device further includes aconfigurable filter adapted to apply de-ringing filtering andde-blocking filtering such as to filter image data retrieved from the atleast one memory unit, whereas the device is adapted to repetitivelydetermine a configuration of the configurable filter in response toreceived image data and to at least one mode selection rule and toconfigure the configurable filter in response to the determination.

The method includes receiving or defining filtering mode selectionrules; receiving image data; and repeating the stages of: (i)determining a configuration of a configurable filter that is adapted toperform de-ringing and de-blocking filtering, in response to thereceived image data and to at least one mode selection rule; (ii)configuring the configurable filter in response to the determination;and (iii) filtering, by the configurable filter, image data.

The configurable filter is capable of performing de-blocking andde-ringing operations, thus there is no need to use different filteringblocks. In addition, many circuits care used for both de-blocking andde-ringing, thus saving integrated circuit real estate.

FIG. 1 illustrates a device 10, according to an embodiment of theinvention. Device 10 can include one or more integrated circuits, caninclude one or more voltage supply units, can be a mobile device such asbut not limited to a cellular phone, a laptop computer, a personal dataaccessory and the like.

Device 10 includes an external memory 420, processor 99 and animage-processing unit (IPU) 200. The processor 99 includes the IPU 200as well as a main processing unit 400. Main processing unit 400 (alsoknown as “general purpose processor”, “digital signal processor” or just“processor”) is capable of executing instructions. It is noted thatdevice 10 can also be connected to some of the illustrated componentsinstead of including these components.

The device 10 can be installed within a cellular phone or other personaldata accessory and facilitate multimedia applications.

The IPU 200 is characterized by a low energy consumption level incomparison to the main processing unit 400, and is capable of performingmultiple tasks without involving the main processing unit 400. The IPU200 can access various memories by utilizing its own image Direct MemoryAccess controller (IDMAC) 280, can support multiple displays of varioustypes (synchronous and asynchronous, having serial interfaces orparallel interfaces), and control and timing capabilities that allow,for example, displaying image frames while preventing image tearing.

The IPU 200 reduces the power consumption of the device 10 byindependently controlling repetitive operations (such as displayrefresh, image capture) that may be repeated over long time periods,while allowing the main processing unit 400 to enter an idle mode ormanage other tasks. In some cases the main processing unit 400participates in the image processing stages (for example if imageencoding is required), but this is not necessarily so.

The IPU 200 components can be utilized for various purposes. Forexample, the IDMAC 280 is used for video capturing, image processing anddata transfer to display. The IPU 200 includes an image converter 230capable of processing image frames from a camera 300, from an internalmemory 430 or an external memory 420.

The device 10 includes multiple components, as well as multipleinstruction, control and data buses. For simplicity of explanation onlymajor data buses as well as a single instruction bus are shown.

According to various embodiment of the invention the IPU 200 is capableof performing various image processing operations, and interfacing withvarious external devices, such as image sensors, camera, displays,encoders and the like. The IPU 200 is much smaller than the mainprocessing unit 400 and consumes less power.

The IPU 200 includes a configurable filter 100 that is capable ofperforming various filtering operations such as de-blocking filtering,de-ringing filtering and the like. Various prior art methods forperforming said filtering operations are known in the art and require noadditional explanation.

The configurable filter 100 can perform de-blocking and de-ringingfiltering operations, according to multiple standards and/orconveniently is capable of performing non-standard filtering operations.By using a single configurable filter the area allocated to the filteris smaller than the area that is required for implementing separatede-ringing and de-blocking filters.

By performing de-blocking filtering operation by configurable filter100, instead of main processing unit 400, the IPU 200 reduces thecomputational load on the main processing unit 400. In one operationalmode the configurable filter 100 can speed up the image processingprocess by operating in parallel to the main processing unit 400.

IPU 200 includes control module 210, sensor interface 220, imageconverter 230, configurable filter 100, IDMAC 280, synchronous displaycontroller 250, asynchronous display controller 260, and displayinterface 270.

The IPU 200 has a first circuitry that may include at least the sensorinterface 220, but may also include additional components such as IDMAC280. The first circuitry is adapted to receive a sequence of imageframes at an update rate (Ur) . The IPU 200 also includes a secondcircuitry that may include at least the asynchronous display controller260.

The sensor interface 220 is connected on one side to an image sensorsuch as camera 300 and on the other side is connected to the imageconverter 230. The display interface 270 is connected to the synchronousdisplay controller (SDC) 250 and in parallel to the asynchronous displaycontroller (ADC) 260. The display interface 270 is adapted to beconnected to multiple devices such as but not limited to TV encoder 310,graphic accelerator 320 and display 330.

The IDMAC 280 facilitates access of various IPU 200 modules to memorybanks such as the internal memory 430 and the external memory 420. TheIDMAC 280 is connected to on one hand to the image converter 230,configurable filter 100, SDC 250 and ADC 260 and on the other hand isconnected to memory interface 410. The memory interface 410 is beconnected to internal memory 430 and additional or alternatively, to anexternal memory 420.

The sensor interface 220 captures image data from camera 300 or from aTV decoder (not shown). The captured image data is arranges as imageframes and can be sent to the image converter 230 for preprocessing orpost processing, but the captured data image can also be sent withoutapplying either of these operations to IDMAC 280 that in turn sends it,via memory interface 410 to internal memory 430 or external memory 420.

The image converter 230 is capable of preprocessing image data from thesensor interface 220 or post-processing image data retrieved from theexternal memory 420 or the internal memory 430. The preprocessingoperations, as well as the post-processing operations includedownsizing, resizing, color space conversion (for example YUV to RGB,RGB to YUV, YUV to another YUV), image rotation, up/down and left/rightflipping of an image and also combining a video image with graphics.

The display interface 270 is capable of arbitrating access to multipledisplays using a time multiplexing scheme. It converts image data formSDC 250, ADC 260 and the main processing unit 400 to a format suitableto the displays that are connected to it. It is also adapted to generatecontrol and timing signals and to provide them to the displays.

The SDC 250 supports displaying video and graphics on synchronousdisplays such as dumb displays and memory-less displays, as well ontelevisions (through TV encoders). The ADC 260 supports displaying videoand graphics on smart displays.

The IDMAC 280 has multiple DMA channels and manages access to theinternal and external memories 430 and 420.

In a typical scenario image data is retrieved from an external memory420 to IDMAC 280, IDMAC 280 sends the image data to the image converter230 in which the image data is post-processed, the image data is thensent to configurable filter 100 to be post-processed and is then sent to(via IDMAC 280) to ADC 260. ADC 260 sends the filtered image data todisplay 330 via display interface 270. It is noted that image data canbe processed in various manners as well as propagate between differentcomponents of device 10.

Those of skill in the art will appreciate that configurable filter 100can be includes within various devices that differ from the exemplarydevice 10 of FIG. 1.

FIG. 2 illustrates a configurable filter 100, according to an embodimentof the invention.

Configurable filter 100 includes a filter flow control unit 190, amemory interface 120, an arithmetic unit 130, a mode decision unit 160,a filter memory controller and a filter memory 110. Conveniently, filtermemory 110 stores data representative of multiple macro-blocks.

Arithmetic unit 130 is connected to filter flow control unit 190, tomemory interface 120, and to mode decision unit 160. Memory interface120 is connected to mode decision unit 160, to filter flow control unit190 and to filter memory 110. Filter memory 110 is further connected toIDMA 280 and to the filter memory controller 140. Filter flow controlunit 190 is further connected to the mode decision unit 160 and tofilter memory controller 140.

A filtering process requires to selectively retrieve portions of imagedata, perform filtering operations and provide filtered portions imagedata. These selective retrieval stages and the relative timings of dataretrieval and filtering operations are usually determined in variousstandards. It is noted that retrieval stages and timings can be alsodefined in non-standard manners. The filter flow control unit 190controls the retrieval process, as well as the timing of data retrievaland filtering operations, by sending control signals to variouscomponents including the memory interface 120, the arithmetic unit 130,the mode decision unit 160 and the filter memory controller 140.

Conveniently, the filter flow control unit 190 includes multiple statemachines that are adapted to control various data retrieval andfiltering sessions. These state machines are denoted 192(1)-192(K). Theinventors used a filter flow control unit 190 that included a MPEG-4post filtering state machine and a H.264 post filtering state machine.The MPEG-4 post filtering state machine interacted with a MPEG-4 columnde-blocking state machine, a MPEG-4 row de-blocking state machine, and aMPEG-4 de-ringing state machine. The H.264 post filtering state machineinteracted with a H.264 row de-blocking state machine, and a H.264column de-blocking machine.

FIG. 3 illustrates a mode decision unit 160, according to an embodimentof the invention.

The mode decision unit 160 includes an initial mode table 162, a modeupdate unit 170, parametric logic 180, decision logic 168, a maskdecoder 166 and a data manipulator 164.

The initial table mode 162 is connected to the mode update unit 170. Themode update unit 170 is connected to the data manipulation unit 164, themask decoder 166, the parametric logic 168 and the decision logic 168.The mask decoder 166 and the data manipulator 164 are also connected tothe decision logic 168.

The decision logic 168 has do decide whether a currently evaluatedfiltering mode is valid or not valid. If it is valid then this is thefiltering mode that should be applied by the arithmetic unit 130. If thefiltering mode is not valid then another filtering mode should beevaluated or the filtering process should stopped.

The decision logic 168 receives as inputs from the data manipulatoroutput signals B0-B9 collectively denoted 152. It receives thresholdparameters P4-P0 collectively denoted 153 from the parametric logic 180.The data manipulator logic 164 receives as input signals I1-I9collectively denoted 164. The parametric logic 180 receives variousparameters as well as input data INT_DATA 119. TABLE 1 illustrates thevalues of B0-B9 and of P4-P0 in response to the selected filtering mode.TABLE 1 defines which information shall be taken into account bydecision logic 168, as further explained below TABLE 1.

MD indicates the filtering mode. Mode 0 does not involve filtering.Modes 1-18 are different MPEG-4 de-blocking filtering modes, modes 19-22are different H.264 luma de-blocking filtering modes, mode 23 is afiltering mode of H.264 chroma de-blocking where Bs=1,2,3, modes 24-27are different filtering modes for H.264 luma de-blocking where Bs=4,mode 28 is a filtering mode for H.264 chroma de-blocking where Bs=4, andmodes 29-33 are different filtering modes for MPEG-4 de-ringing.

TABLE 1 Threshold parameters Data manipulator output Mask MD P4 P3 P2 P1P0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 M 0 X X X X X X X X X X X X X X X X 1 XX QPB1 QPB2 QPB1 X X X X I6 I5 I5 I4 I4 I3 0 2 X X QPB2 QPB3 QPB2 X X XX I6 I5 I5 I4 I4 I3 7 3 X X X X 2QP X X X X X X X X I0 I1 7 4 X X X X2QP X X X X X X X X I0 I2 1 5 X X X X 2QP X X X X X X X X I1 I3 1 6 X XX X 2QP X X X X X X X X I2 I4 1 7 X X X X 2QP X X X X X X X X I3 I5 1 8X X X X 2QP X X X X X X X X I4 I6 1 9 X X X X 2QP X X X X X X X X I5 I71 10 X X X X 2QP X X X X X X X X I2 I4 1 11 X X X X 2QP X X X X X X X XI3 I5 1 12 X X X X 2QP X X X X X X X X I4 I6 1 13 X X X X 2QP X X X X XX X X I5 I7 1 14 X X X X 2QP X X X X X X X X I6 I8 1 15 X X X X 2QP X XX X X X X X I7 I9 1 16 X X X X 2QP X X X X X X X X I8 I9 1 17 X X 4QP4QP 4QP X X X X I4 I0 I9 I5 I7 I2 7 18 X X 4QP 4QP 4QP X X X X I4 I0 I9I5 I7 I2 7 19 β β β β A I4 I6 I1 I3 I2 I3 I5 I4 I3 I4 7 20 β β X β β I4I6 I1 I3 X X I1 I3 I6 I4 3 21 β β X X β I4 I6 I1 I3 X X X X I3 I1 1 22 ββ X β X I4 I6 I1 I3 X X I6 I4 X X 2 23 X X β β α X X X X I2 I3 I5 I4 I3I4 7 24 X X β β αU X X X X I2 I2 I5 I4 I3 I4 7 25 X X β β αU X X X X I1I3 I6 I4 I3 I4 7 26 X X X β αU X X X X X X I3 I1 I3 I4 3 27 X X β X αU XX X X I6 I4 X X I3 I4 5 28 X X β β α X X X X I2 I3 I5 I4 I3 I4 15 29 XQP2 QP2 QP1 QP1 I5 I3 I5 I3 I7 I1 I3 I4 I1 I4 15 30 X QP2 QP2 QP1 QP1 I5I3 I5 I3 I7 I1 I3 I4 I1 I4 15 31 X QP2 QP2 QP1 QP1 I5 I3 I5 I3 I7 I1 I3I4 I1 I4 15 32 X QP2 QP2 QP1 QP1 I5 I3 I5 I3 I7 I1 I3 I4 I1 I4 15 33 X XX X X X X X X X X X X X X 0

Conveniently, the decision involves selecting one condition out ofmultiple conditions and determining if the selected condition isfulfilled. The following equations represent three exemplary conditions:

-   -   (i) |B0-B11|<P0 and |B2-B3|<P1;    -   (ii) |B0-B1|<P0 and |B2-B3|<P1 and |B4-B5|<P2;    -   (iii) |B0-B1|<P0 and |B2-B3|<P1 and |B4-B5|<P2 and |B7-B7|<P3.

If one of the conditions is fulfilled then decision logic 168 negatesMODE_UPDATE 151, else this signal is asserted. This signal is providedto mode update unit 170 that in turn determines whether to retrievesuccessful evaluation filter mode information (if MODE_UPDATE 151indicates that the mode is valid) or to retrieve failed evaluationfilter mode information (if MODE_UPDATE 151 indicates that theevaluation failed).

The mode update unit 170 outputs SELECTED_FILTER_MODE 152 to thearithmetic unit 130 to indicate what is the selected filtering mode, andalso outputs FILTER_MODE 150 to the mask decoder 166, parametric logic180 and data manipulator 164 to indicate the next filtering mode to beevaluated. If the value of the failed evaluation filter mode informationis zero the evaluation ends and no filtering process is applied.

If the evaluation is successful than both SELECTED_FILTER_MODE 152 andFILTER_MODE 150 will indicate what is the selected filtering mode.

The mask decoder 166 receives the FILTER_MODE 150 signal and indicates(this indication is sent to decision logic 168) which one of equations(i)-(iii) to check.

FIG. 4 illustrates mode update unit 170, according to an embodiment ofthe invention.

Mode update unit 170 includes modes lookup table 172 that storessuccessful evaluation filter mode information and failed evaluationfilter mode information. Each entry of table 172 corresponds to adifferent filtering mode out of modes zero to J. FIG. 4 illustrates athirty four entry table (J equals 33) but this is not necessarily so.Each entry includes successful evaluation filter mode information173(1)-173(33) and also a failed evaluation filter mode information174(1)-174(33). The former indicates a selected valid filtering mode andthe latter indicates the next filtering mode to be evaluated, if anevaluation of a current filtering mode failed.

An exemplary modes lookup table is illustrated below:

TABLE 2 Entry True False Filtering process number (j) 173(j) 174(j) Nofiltering 0 0 0 MPEG-4 de-blocking 1 1 2 2 2 0 3 3 0 4 4 0 5 5 0 6 6 0 77 0 8 8 0 9 9 0 10 10 0 11 11 0 12 12 0 13 13 0 14 14 0 15 15 0 16 16 017 17 0 18 18 0 H.264 luma de-blocking 19 19 0 Bs = 1, 2, 3 20 20 21 2121 22 22 22 19 H.264 chroma de-blocking 23 23 0 Bs = 1, 2, 3 H.264 lumade-blocking 24 24 0 Bs = 4 25 25 26 26 26 27 27 27 24 H.264 chromade-blocking 28 28 0 Bs = 4 MPEG-4 de-ringing 29 29 30 30 30 31 31 31 3232 32 33 33 33 33

Each entry of table 172 is connected to a multiplexer M1 175 thatselects which entry to retrieve in response to the value (j) ofFILTER_MODE 150. The jth successful evaluation filter mode information173(j) and the jth failed evaluation filter mode information 174(j) areprovided to a second multiplexer M2 176 that selected between theseinformation in response to the value of MODE_UPDATE 151.

The output of M2 167 provided output signal SELECTED_FILTER_MODE 152.The output of M2 167 us also connected to one inputs of multiplexer M3177, Other inputs of multiplexer M3 177 receive an INITIAL FILTERINGMODE signal 156 which provides an indication on an initial filteringmode information (INITIAL_FILTERING_MODE 156). The initial filteringmode information is selected during initialization stages of filter 100.

The selection between various signals that are provided to M3 177 isdone by select signal 159 provided by filter flow control unit 190.

FIG. 5 illustrates arithmetic unit 130, according to an embodiment ofthe invention.

The arithmetic unit 130 includes multiple filter coefficient lookuptables (131(1)-131(J)) that form a filter coefficient bank 131. If thej'th filtering mode is selected then the 131(j) filter coefficientlookup table is retrieved from the filter coefficient bank 131 and isused to configure the multiple add-subtract circuits (70, 71, 77, 78,79). as well as to provide various filter coefficients (such as CF0-CF920-29, OFFSET 81, MIN 82, MAX 83,) that affect the value (P_VAL 86) ofthe filtered pixel.

Arithmetic unit 130 includes multiple add-subtract circuits AS1 61, AS262, AS7 67, AS8 68, and AS9 69. Each add-subtract circuit can act as anadder or as a subtracting circuit in response to a control signal. Thus,each add-subtract circuit adds the first input to a second input (whenit acts as an adder) or subtracts the second input from the first input(when it acts as a subtracting circuit). The second input is denoted bya “+” symbol.

Arithmetic unit 130 also includes: (i) multiplexers MUX2 32, MUX3 33,MUX4 34, MUX5 35, MUX7 37, MUX8 38 and MUX9 39; (ii) multipliers M0 40,M1 41, M3 43 and M4 44; (iii) adders A1 51, A2 52, A3 53 and A4 54; and(iv) clipping unit 90 and register 92. Clipping unit 90 provides aclipped value that ranges between MIN 82 and MAX 83.

Arithmetic unit 130 receives multiple coefficients CF0-CF9 20-29, OFFSET81, MIN 82, MAX 83, and RSFT 84 from a the j'th coefficient look uptable 131(j) within the arithmetic unit 130, v0-v9 10-19 from memoryinterface 120 as well as additional control signals such as Cycle_countsignal (not shown) that counts the pixels that are filtered by thearithmetic unit 130. Te filtering process can apply different filters toeach pixel.

TABLE 3 illustrates the connectivity of various components of arithmeticunit 130.

TABLE 3 Cir. 1^(st) input 2^(nd) input 3^(rd) input 4^(th) input cntoutput M4 V9 CF9 1^(st) input A2 MUX8 P_VAL V8 V8 0 CF8 2^(nd) input A2A2 M4 MUX8 1^(st) input AS7 AS7 A2 OFFSET AS7C 1^(st) input AS9 AS9 AS7AS8 AS9C MUX39 MUX39 AS9 AS9 AS9 AS9 REFT CLIP CLIP MUX9 MIX MIN REG REGCLIP P_RDY P_VAL M3 V6 CF6 1^(st) input A1 MUX7 V7 V7 V7 0 CF7 2^(nd)input A1 A1 M3 MUX7 1^(st) input A4 A4 A1 AS2 2^(nd) input AS8 MUX5 V5V5 V5 0 CF5 2^(nd) input AS2 MUX4 V4 V4 V4 0 C45 1^(st) input AS2 AS2MUX4 MUX5 AS2C 2^(nd) input A4 AS8 A3 AS2 AS8C 2^(nd) input AS9 M0 V0CF0 1^(st) input AS0 M1 V1 CF1 2^(nd) input AS0 AS0 M0 M1 AS0C 1^(st)input A3 A3 AS0 AS1 1^(st) input AS8 MUX3 0 V3 V3 V3 CF3 2^(nd) inputAS1 MUX2 0 V2 V2 V2 CF2 1^(st) input AS1 AS1 MUX2 MUX3 AS1C 2^(nd) inputA3

Register REG 92 provides a pixel value signal P_VAL 86 at a timingdetermining by a pixel ready signal (P_RDY 87).

In most cases the coefficients equaled zero, although in some casestheir values also was 1,2,3 and 4.

FIG. 6 illustrates memory interface 120, according to an embodiment ofthe invention.

Memory interface 120 receives image data and manipulates it to providevarious signals to the arithmetic unit 130 (V0-V9 10-19) and to the modedecision unit (I0-I9 154).

The memory interface 120 includes a read path and a write path. Thewrite path includes multiplexers WMUX1-WMUX2 125-126. The read pathincludes shift registers SR1 129 and SR2 128, and read multiplexersRMUX1-RMUX4 121-124. The memory interface 120 and especially the readpath perform data manipulations and can provide output signals that areresponsive to current image data as well as pervious image data.

RMUX1 121 receives as input a sixty-four bits wide input data INT_DATA119. It outputs eight bits that are selected in response to aRD_BYTE_SEL 111 signal.

RMUX1 122 receives two one-hundred and twenty eight bits wide inputs.The first input receives sixty four bits of INT_DATA 119, multiple zerobits and sixty four bits of previous image data from shift register SR1129. The second input receives the byte from RMUX1 121, multiple zerobits and one hundred and twenty bits of previous image data from shiftregister SR1 129.

RMUX2 122 receives two inputs, each of two hundred and forty bits. Afirst input of RMUX2 122 eight bits of the output of RMUX 121, onehundred and twenty bits from the output of SR1 129 and one hundred andten zeros. A second input of RMUX2 122 receives sixty four bits ofINT_DATA 119, sixty four bits from the output of SR1 129 and one hundredand ten zeros.

Shift register SR1 outputs multiple partially overlapping groups offorty bits denoted RDI_0-RDI_29. Some are sent back to the inputs ofRMUX2 122 and some are provided to RMUX2 124 and WMUX1 125.

RMUX3 123 is controller by signal RD_DATA_SHIFT 113 provided by unit190. Eighty output bits of SR1 129 are provided as V9-V0 to arithmeticunit 130.

SR2 129 is controlled by a control signals that performs shiftingoperations. It receives as input sixty four bits of INT_DATA 119 andforty bits from its output.

A first input of RMUX4 124 receives eighty bits from shift register SR2128. A second input of RMUX4 124 receives seventy two bits from shiftregister SR2 128 and eight bits from the output of RMUX3 123. A thirdinput of RMUX4 124 receives eighty bits from the output of RMUX3 123.One of these inputs are selected by MD_SRC_SEL 114 and is provided asI0-I9 154 to mode decision unit 160.

WMUX1 125 receives as input eighty bits of V9-V0 and selects only eightbits (according to control signal WDATA_SEL 115). These eight bits areprovided to a first input of WMUX2 126. The second input of WMUX2 126receives P_VAL 86. WMUX2 126 selects between these signals in responseto WDATA_SRC_SEL 116 signal.

FIG. 7 is a flow chart of a method 600 for filtering image data,according to an embodiment of the invention.

Method 600 starts by stage 610 of receiving or defining filtering modeselection rules. The filtering mode selection rules can include, forexample, filtering mode evaluation rules (for example equations(i)-(iii), the decisions illustrated in TABLE 1) the modes lookup table,and the like.

Stage 610 is followed by stage 620 of receiving image data. Referring tothe example set forth in FIG. 1 and in FIG. 2, relatively large amountsof image data is received and stored within internal memory 430 and/orexternal memory 420. Smaller portions of image data that are used duringthe filtering process are stored in filter memory 110 and that areselectively provided to the arithmetic unit 130 and mode decision unit160 by memory interface 120.

Stage 620 is followed by stage 630 of determining a configuration of aconfigurable filter that is adapted to perform de-ringing andde-blocking filtering, in response to the received image data and to atleast one mode selection rule. Referring to the examples set forth inFIG. 2-FIG. 4 the determination can include one or more iterations ofevaluating a filtering mode (for example by mode decision unit 160), andin response to the result of the evaluation either declaring anevaluated mode Stage 630 is followed by stage 640 of configuring theconfigurable filter in response to the determination.

For example, selected coefficients such as CF0-CF9 10-19 are provided toarithmetic unit 130. In addition the various add-subtract units are setto perform addition or subtraction operations.

Conveniently, stage 630 includes stage 632 of evaluating a filteringmode; and stage 643 of determining whether to select the filtering mode,to evaluate another filtering mode or determine not to perform afiltering operation in response to at least one mode selection rule.Conveniently, stage 634 includes selecting between successful evaluationfilter mode information and failed evaluation filter mode information.For example, the content of the mode lookup table can be selectivelyretrieves and a selection between failed or successful evaluation filtermode information 174(J) or 173(J) accordingly. If a new filtering modeis going to be evaluated stage 634 is followed by stage 436 of selectinga new filtering mode and then jumping to stage 632. The selection can beimplemented, for example, by checking the information retrieved from themodes table.

Conveniently, stage 630 includes selecting a filtering control statemachine out of multiple control state machines. It is noted that thisstage can occur before stage 620, in parallel to stage 630 and the like.Referring to the example set forth in FIG. 5, the selection may includeselecting a state machine out of: (i) MPEG-4 post filtering statemachine, (ii) MPEG-4 column de-blocking state machine, (iii) MPEG-4 rowde-blocking state machine, (iv) MPEG-4 de-ringing state machine, (v)H.264 post filtering state machine, (vi) H.264 row de-blocking statemachine, and (vii) H.264 column de-blocking state machine.

Conveniently, stage 630 includes selecting a filter coefficient lookuptable out of multiple filter coefficient lookup table. In such a casestage 640 may include retrieving filter coefficients from the selectedfilter coefficient lookup table.

Stage 640 is followed by stage 650 of filtering, by the configurablefilter, image data. The filter can be configured differently afterfiltering one or more pixels, after filtering one or more macroblocksand the like.

Conveniently, stages 630 and 650 include manipulating current image dataand previous image data.

Stage 650 is followed by stage 660 of determining whether the image datashould be filtered by another filtering mode (for example—if ade-blocking algorithm was applied—should the configurable filter performde-ringing filtering). If the answer is positive stage 660 is followedby stage 630. Else, stage 660 is followed by stage 620.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A method for filtering image data, the method comprises receiving ordefining filtering mode selection rules; and receiving image data;repeating the stages of: determining a configuration of a configurablefilter that is adapted to perform de-ringing and de-blocking filtering,in response to the received image data and to at least one modeselection rule; configuring the configurable filter in response to thedetermination; and filtering, by the configurable filter, image data. 2.The method according to claim 1 wherein the determining comprisesevaluating a filtering mode; and determining whether to select thefiltering mode, to evaluate another filtering mode or determine not toperform a filtering operation in response to at least one mode selectionrule.
 3. The method according to claim 2 wherein the determiningcomprises selecting between a successful evaluation filter modeinformation and a failed evaluation filter mode information.
 4. Themethod according to claim 1, wherein the filtering and the determiningcomprise manipulating current image data and previous image data.
 5. Themethod according to claim 1, wherein the configuring comprisesconfiguring multiple add-subtract circuits.
 6. The method according toclaim 1, wherein the determining comprises selecting filter coefficientlookup table out of multiple filter coefficient lookup table, andwherein the configuring comprises retrieving filter coefficients fromthe selected filter coefficient lookup table.
 7. The method according toclaim 1, wherein the determining further comprises selecting a filteringcontrol state machine out of multiple control state machines.
 8. Themethod according to claim 1, wherein one or more repetitions of thefiltering comprise de-ringing filtering and wherein one or morerepetitions of the filtering comprise de-blocking filtering.
 9. A devicecomprising: at least one memory unit adapted to store image data; aconfigurable filter adapted to apply de-ringing filtering andde-blocking filtering such as to filter image data retrieved from the atleast one memory unit wherein the device is adapted to repetitivelydetermine a configuration of the configurable filter in response toreceived image data and to at least one mode selection rule and toconfigure the configurable filter in response to the determination. 10.The device according to claim 9 wherein the device is adapted toevaluate a filtering mode; and to determine whether to select thefiltering mode, to evaluate another filtering mode or determine not toperform a filtering operation in response to at least one mode selectionrule.
 11. The device according to claim 10 further adapted to selectbetween a successful evaluation filter mode information and a failedevaluation filter mode information.
 12. The device according to claim 9,wherein the configurable filter is adapted to manipulate current imagedata and previous image data.
 13. The device according to claim 9,wherein the configurable filter comprises multiple configurableadd-subtract circuits.
 14. The device according to claim 9, wherein thedevice is comprises multiple filter coefficient lookup tables, andwherein the device is adapted to retrieve filter coefficients from aselected filter coefficient lookup table.
 15. The device accord to claim9, wherein the configurable filter comprises multiple filter controlstate machines.
 16. The device accord to claim wherein the device isadapted to serially perform de-blocking filtering and de-ringingfiltering by the configurable filter.
 17. The method according to claim2, wherein the filtering and the determining comprise manipulatingcurrent image data and previous image data.
 18. The method according toclaim 2, wherein the configuring comprises configuring multipleadd-subtract circuits.
 19. The device according to claim 10, wherein theconfigurable filter is adapted to manipulate current image data andprevious image data.
 20. The device according to claim 10, wherein theconfigurable filter comprises multiple configurable add-subtractcircuits.